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ZY1207 7A No-Bus POL Data Sheet
3V to 14V Input ? 0.5V to 5.5V Output
4.
Electrical Specifications
Specifications apply at the input voltage from 3V to 14V, output load from 0 to 7A, ambient temperature from -40°C
to 85°C, output capacitance consisting of 110 ? F ceramic and 220 ? F tantalum, and default performance
parameters settings unless otherwise noted.
4.1
Input Specifications
Parameter
Input voltage (V IN )
Input Current (at no load)
Undervoltage Lockout (VLDO
connected to VIN)
Undervoltage Lockout (VLDO
connected to V AUX =5V)
External Low Voltage Supply
VLDO Input Current
Conditions/Description
At V IN <4.75V, VLDO pin needs to be
connected to an external voltage source
higher than 4.75V
V IN ? 4.75V, VLDO pin connected to VIN
Ramping Up
Ramping Down
Ramping Up
Ramping Down
Connect to VLDO pin when V IN <4.75V
Current drawn from the external low
voltage supply at VLDO=5V
Min
3
4.75
Nom
50
4.00
3.9
2.8
2.7
50
Max
14
14
Units
VDC
mADC
VDC
VDC
VDC
VDC
VDC
mADC
4.2
Output Specifications
-7
Parameter
Output Current (I OUT )
Output Voltage Range (V OUT )
Conditions/Description
V IN MIN to V IN MAX
Programmable 2 with a resistor between
TRIM and REF pins
Default (no resistor)
Min
1
0.5
Nom
0.5
Max
7
5.5
Units
ADC
VDC
VDC
Output Voltage Setpoint
Accuracy 3
V IN =12V, I OUT =0.5*I OUT MAX , room
temperature
See Ordering Information
Line Regulation 3
V IN MIN to V IN MAX
±0.2
%V OUT
Load Regulation
3
0 to I OUT MAX
±0.2
%V OUT
Dynamic Regulation
Peak Deviation
Peak Deviation
Settling Time
Output Voltage Peak-to-Peak
Ripple and Noise
BW=20MHz
Full Load
Temperature Coefficient
Slew rate 1A/ ? s, 50-75% load step,
V IN ≥ 5V
V IN =3.3V
to 10% of peak deviation
V IN =5.0V, V OUT ≤ 2.5V
V IN =5.0V, V OUT >2.5V
V IN =12V, V OUT ≤ 2.5V
V IN =12V, V OUT >2.5V
V IN =12V, I OUT =0.5*I OUT MAX
75
100
30
15
25
25
40
50
mV
mV
? s
mV
mV
mV
mV
ppm/°C
Switching Frequency
450
500
550
kHz
1
At the negative output current (bus terminator mode) efficiency of the ZY1207 degrades resulting in increased internal power dissipation.
ZY1207 is a step-down converter, thus the output voltage is always lower than the input voltage as show in Figure 1.
Digital PWM has an inherent quantization uncertainty of ±6.25mV that is not included in the specified static regulation parameters.
Therefore maximum allowable negative current under specific conditions is 20% lower than the current determined from the derating curves
shown in paragraph 5.5.
2
3
ZD-00697 Rev. 1.9, 24-Jun-10
www.power-one.com
Page 3 of 18
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